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Directions · CHIPS AND NETWORK

Semiconductors and accelerators

In one viewAI hardware stopped being a graphics card. It is now a rack of several specialised chips working as one enormous machine.

The platform is designed as a whole: CPU, accelerator, switches and network chips built together. In parallel, every hyperscaler is building its own.

Status
TypeDirections
Marker
Events in dossier7
Development chronology

Researched

2026-01-06

NVIDIA Vera Rubin

About this eventSix new chips as one AI supercomputer: Vera CPU, Rubin GPU, NVLink 6, ConnectX-9, BlueField-4, Spectrum-6.

2026-03-11

Meta MTIA 300

About this eventMeta said its new accelerator is already in production and is the first of four in-house silicon generations being deployed over two years.

2026-03

Rubin in production

About this eventBy GTC 2026 the platform grew to seven chips in production; partner availability lands in H2.

In progress

barrier

Memory is the shortage

About this eventThe bottleneck shifted from compute to data delivery: 2026 server demand is constrained by DRAM and NAND supply, while most HBM3E capacity was allocated in advance.

Planned

planned

Optics between racks

About this eventCopper can no longer carry the required connectivity — interconnects move to light.

Distant horizons

ahead

A chip for one model

About this eventSilicon designed for a single architecture rather than a class of tasks: multiples of efficiency at the price of total inflexibility.

Sources and research

Primary material behind this dossier: papers, lab publications and official reports.

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